VHDL Modeling for Digital Design Synthesis

Name: VHDL Modeling for Digital Design Synthesis
Brand: Springer Nature
SKU: 9781461523437
Availability: InStock

Best Price (Coupon Required):
Buy VHDL Modeling for Digital Design Synthesis for $152.10 at @ Link.springer.com when you apply the 10% OFF coupon at checkout.
Click “Get Coupon & Buy” to copy the code and unlock the deal.

Set a price drop alert to never miss an offer.

1 Offer Price Range: $169.00 - $169.00

BEST PRICE

Single Product Purchase

$152.10

@ Link.springer.com with extra coupon

Price Comparison

Seller	Contact Seller	List Price	On Sale	Shipping	Best Promo	Final Price	Volume Discount	Financing	Availability	Seller's Page
BEST PRICE 1 Product Purchase @ Link.springer.com		$169.00	$169.00		10% OFF This deals requires coupon	$152.10		See Site	In stock	Visit Store

Product Details

Brand

Springer Nature

Manufacturer

N/A

Part Number

GTIN

9781461523437

Condition

New

Product Description

The purpose of this book is to introduce VHSIC Hardware Description Lan guage (VHDL) and its use for synthesis. VHDL is a hardware description language which provides a means of specifying a digital system over different levels of abstraction. It supports behavior specification during the early stages of a design process and structural specification during the later implementation stages. VHDL was originally introduced as a hardware description language that per mitted the simulation of digital designs. It is now increasingly used for design specifications that are given as the input to synthesis tools which translate the specifications into netlists from which the physical systems can be built. One problem with this use of VHDL is that not all of its constructs are useful in synthesis. The specification of delay in signal assignments does not have a clear meaning in synthesis, where delays have already been determined by the im plementationtechnolo~y. VHDL has data-structures such as files and pointers, useful for simulation purposes but not for actual synthesis. As a result synthe sis tools accept only subsets of VHDL. This book tries to cover the synthesis aspect of VHDL, while keeping the simulation-specifics to a minimum. This book is suitable for working professionals as well as for graduate or under graduate study. Readers can view this book as a way to get acquainted with VHDL and how it can be used in modeling of digital designs.

Available Colors

N/A

Available Sizes

N/A