Formal Semantics and Proof Techniques for Optimizing VHDL Models

Name: Formal Semantics and Proof Techniques for Optimizing VHDL Models
Brand: Springer Nature
SKU: 9781461551232
Availability: InStock

Best Price (Coupon Required):
Buy Formal Semantics and Proof Techniques for Optimizing VHDL Models for $76.50 at @ Link.springer.com when you apply the 10% OFF coupon at checkout.
Click “Get Coupon & Buy” to copy the code and unlock the deal.

Set a price drop alert to never miss an offer.

1 Offer Price Range: $84.99 - $84.99

BEST PRICE

Single Product Purchase

$76.50

@ Link.springer.com with extra coupon

Price Comparison

Seller	Contact Seller	List Price	On Sale	Shipping	Best Promo	Final Price	Volume Discount	Financing	Availability	Seller's Page
BEST PRICE 1 Product Purchase @ Link.springer.com		$84.99	$84.99		10% OFF This deals requires coupon	$76.50		See Site	In stock	Visit Store

Product Details

Brand

Springer Nature

Manufacturer

N/A

Part Number

GTIN

9781461551232

Condition

New

Product Description

Formal Semantics and Proof Techniques for Optimizing VHDL Models presents a formal model of VHDL that clearly specifies both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL. The dynamic semantics is presented as a description of what the simulation of VHDL means. In particular it specifies what values the signals of a VHDL description will take if the description were to be executed. An advantage of the approach is that the semantic model can be used to validate different simulation algorithms. The book also presents an embedding of the dynamic semantics in a proof checker which is then used to prove equivalences of classes of VHDL descriptions. Formal Semantics and Proof Techniques for Optimizing VHDL Models is written for hardware designers who are interested in the formal semantics of VHDL.

Available Colors

N/A

Available Sizes

N/A