Designing Reliable and Efficient Networks on Chips

Name: Designing Reliable and Efficient Networks on Chips
Brand: Springer Nature
SKU: 9781402097560
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Springer Nature

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9781402097560

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Product Description

Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another important design challenge for NoCs will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. The purpose of Designing Reliable and Efficient Networks on Chips is to provide state-of-the-art methods to solve some of the most important and time-intensive problems encountered during NoC design.

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